EDN

An overview of SystemVerilog 3.1

SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along ...
Electronic Design

Verify SoCs Faster And More Predictably With SystemVerilog And Constrained-Random Stimuli

Verifying the integration and operation of new IP in a legacy system-on-a-chip (SoC) becomes challenging. This is true particularly when the legacy SoC environment was built using a directed test ...
Design-Reuse

A SystemVerilog DPI Framework for Reusable Transaction Level Testing, Debug and Analysis of SoC Designs

Complex system design requires modeling, testing, debug and analysis of many levels of abstraction with varying levels of accuracy. Reuse from previous steps is important at each step of the design ...
Design-Reuse

Avery rolls automation tool, simulator into one

ANDOVER, Mass. — Avery Design Systems has folded a Verilog and C-language testbench-automation tool that works with third-party simulators into its TestWizard offering. The capability had been bundled ...