EDN

Physical design team tackles challenging SoC

When describing the complexity of deep sub-micron systems on chip (SoCs), most engineers and their managers tend to refer to a combination of gate count, amount of embedded memory, and frequency of ...
EDN

Addressing mixed-signal SoC physical design challenges

Design teams have adopted the mixed signal simulation flow to address the increased demand for mixed mode functionality on a single chip. The physical design environment could benefit from a similar ...
Semiconductor Engineering

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster

Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a ...
Electronic Design

Optimize SoC Design with a Network-on-Chip Strategy

How third-party interconnect IP saves time, lowers risk, and speeds completion. NoC is the predominant SoC interconnect strategy. NoC IP accommodates multiple interconnect protocols and data widths.
Semiconductor Engineering

Fast-Track Your Early SoC Design Exploration And Verification

Most advanced node system-on-chip (SoC) designs are very large, and very complex. They typically contain many blocks and intellectual property (IP) that perform specialized functions, such as ...
Electronic Design

Physically Aware Network-on-Chip Streamlines SoC Design Cycle

This video is part of TechXchange Talks. Arteris IP has released FlexNoC 5, a network-on-chip (NoC) IP configuration tool, designed to improve system-on-chip (SoC) designs and streamline the design ...
Business Wire

Silicon Topology Joins TSMC Design Center Alliance (DCA)

HSINCHU, Taiwan--(BUSINESS WIRE)--Silicon Topology, a Taiwan-based leading ASIC/SoC physical layout design service provider, today announced that it has joined the Design Center Alliance (DCA) of TSMC ...
Embedded

Reducing signoff corners to achieve faster 40 nm SOC design closure

In the race to achieve high design performance and stringent power requirements, the VLSI world is moving quickly down the scaling curve to process technologies that ...
Deccan Chronicle

From Challenge to Breakthrough: Srikanth Aitha's SoC Optimization Success Story

In the complex world of high-performance semiconductor design, where timing closure and power optimization challenges can derail even the most promising projects, the remarkable transformation of a ...
Design-Reuse

AI in VLSI Physical Design: Opportunities and Challenges

As semiconductor technology pushes the boundaries of scale and complexity, traditional VLSI physical design methodologies are struggling to keep pace. The rise of Artificial Intelligence (AI), ...