Design-Reuse

Greater Debug of a SoC having heterogeneous ARM Core's

In today’s world of smart and high end gadgets, devices serving variety of features is only made possible by having more than a single core. Having more than a single core results in rise of output ...
Design-Reuse

Debug IP for SoC Debug

Any developer, but above all the firmware or software developer, building a complex, microprocessor-based embedded product faces an enormous challenge to get a reliable, high performance product to ...
Embedded

Defining standard Debug Interface Socket requirements for OCP-Compliant multicore SoCs: Part 1

Enabling a robust on-chip debug capability is being recognized as animportant Design for Debug (DFD) capability for complex SoC and having DFDstandardization makes the Open Core Protocol (OCP) ...
EDN

Bridge software and hardware to accelerate SoC validation

Asthe SoC (systems-on-chip) complexity continues to increase, it is nolonger possible to ignore the challenges caused by the convergence ofsoftware and hardware development. These highly functional ...
Electronic Design

Eradicate Hardware And Software Bugs On Multicore SoCs

Able to debug complex SoC designs, this powerful emulator leverages a common JTAG port to diagnose software running in multiple deeply embedded processors. System-on-a-chip (SoC) designs have emerged ...
EDN

ARM intrusive debugging for post-silicon SoC validation

Debugging large RTL projects has become increasingly complex. With different types of applications evolving, there is a need for different ways to enable debug hooks in every application. Although the ...